Since the August 2017 eclipse, Pavel has made numerous improvements to the FPGA firmware and associated C code. The particularly interesting changes are those enabling easy GPS 1PPS input. An interesting question is does the clock synchronize to 1PPS or instead tag the data at the pulse? It seems the latter is more likely at first guess.
The team started with Pavel’s radar project.
The basic idea is to:
- setup a virtual machine
- install Vivado
- compile & create an SD card image like the LED blinker example
Pavel’s commit adds the trigger logic to the radar projects. However, we experienced build errors at the lines:
The server outputs
Bus error when it reaches these lines.
It stems from the sts (status) AXI, communication pathway.
I am thinking of rebuilding our team VM in case I have a different version of something.
The error that you observe is expected. The radar.c code should be modified to adapt it to the radar FPGA configuration. In its current state, radar.c is mostly a copy of a code from one of my SDR project that I never tested with the radar FPGA configuration.